Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to read-only memory (ROM), which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively. Other types of non-volatile memory include, but are not limited to, Polymer Memory, Ferroelectric Random Access Memory (FeRAM), Ovionics Unified Memory (OUM), Nitride Read Only Memory (NROM), and Magnetoresistive Random Access Memory (MRAM).
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that is typically erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks.” The memory cells of a Flash memory array are typically arranged into a “NOR” architecture (each cell directly coupled to a bit line) or a “NAND” architecture (cells coupled into “strings” of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access). Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
Each erase block of a Flash memory device typically contains user data areas and overhead data areas. The overhead data areas contain overhead information for operation of the erase block and/or the user data area the overhead data space is associated with. Such overhead information typically includes, but is not limited to, erase block management (EBM) data, sector status information, or an error correction code (ECC). In some Flash memory devices each erase block is divided into a series of logical sectors, where the logical sectors each generally contain 512 bytes of user data space and an associated control or overhead area. One or more of the logical sectors are each typically written to a single row of the Flash memory array (also known as a physical page) within the erase block.
In memory and memory systems, ECC's allow errors in the data stored in the memory to be detected and in many cases corrected. ECC codes include block codes, that are associated with a block of stored data (such as a memory data segment, a memory data block, or a memory data sector), and stream codes, that are typically utilized with streams of transmitted data. ECC codes include, but are not limited to, Hamming codes, Reed-Solomon (R-S) codes, Bose-Chaudhuri-Hochquenghem (BCH) codes, circular redundancy check codes (CRC-32), Golay codes, Reed-Muller codes, Goppa codes, and Denniston codes. In most memories and memory systems, error detection is accomplished via a dedicated ECC check hardware (referred to herein as ECC generators or ECC generator/checkers) as the data is read out. Unlike error detection, error correction is typically a more difficult process and generally involves a time consuming algorithmic process. As a result, error correction of data that has been detected as corrupt is generally done by a microprocessor or specialized hardware.
The prevalence of errors in modern memory devices, and in non-volatile and Flash memory devices in particular, have been tending to increase with smaller device sizes, increased array density, and lower operating voltages. In addition, increased active usage of non-volatile memory devices in electronic devices has tended to increase the incidence of operationally induced failures in these devices over long periods of active use due to due to physical damage, impurity migration, write fatigue, electrical transients, etc. This increased number of errors and the time consuming nature of using an ECC correction algorithm to correct errors combine in modern high speed memory devices to affect memory operation and speed; slowing the data rate of the memory device or memory system as these errors are corrected.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved ECC apparatus and methods that allows for fast and easy correction of data memories.